RegiRAM

RegiRAM : Bridging the Performance Gap Between Logic and Memory

RegiRAM (Register RAM) is high density (multiple megabit), static memory that performs like a register file in speed, flexibility, and robustness. RegiRAM, like a register file, scales accordingly with logic as process technology progresses as shown in the figure below

Key RegiRAM Features:

· Sub-nanosecond access time with zero latency
· Fully static, consumes little DC power
· Consumes as little as one tenth of active power as conventional SRAM
· Macro density is 1.5 to 2 times 6T/8T
· Compiler-generated macros
· Multiple-port Capable
· ECC and/or redundancy options available for repair

RegiRAM offers three times the performance, one-tenth the power, and up to two times higher density than the conventional 6T/8T single/dual port SRAM, and is ideal for System-On-Chip applications in Communications, Networking, Computing, and Consumer products.

Unlike conventional memory that turns on the entire word line when reading data from memory cells, RegiRAM activates only very small amount of memory cells so the power consumption is extremely low and is essentially independent of the memory density used.

Design Flexibility

With its multiple-port capability, RegiRAM is especially ideal for those products which call for increasing demand of higher data throughput, and greater bandwidth, as in networking and high performance graphic applications.

RegiRAM's flexibility also lies in its capability of achieving unprecedented peripheral efficiency even in distributed, small (Kb) memory blocks of different configurations. Other high-density memory solutions in the market not only become area-inefficient, when density becomes less than 1Mb, but also lacking in multiple-port capability.

Superior Reliability

Employing RegiRAM's unique register-file-like characteristics, differential sensing has been completely eliminated from the design, such that no sense amplifier is needed inside the memory. This results is a superior tolerance to noise, making RegiRAM far more robust and reliable than the conventional SRAM.

RegiRAM also offers UniRAM's patented high performance ECC (Error Correction Code) circuit, which is capable of correcting data within one nanosecond of processing time, as an option for soft error recovery, making RegiRAM virtually immune to soft errors.

Low Cost of Ownership

With RegiRAM's ultra-high performance and ease of use, design complexity is dramatically reduced. Consequently, gate counts for glue logic, data paths, and buffers are also significantly reduced. This translates to die size reduction above and beyond that of a smaller memory macro area.

RegiRAM uses standard logic process with no special process requirements, meaning no production cost adder over logic wafers.

Compiler-Based

RegiRAM macros are compiler-generated, and optimized for performance and density. Compiler-produced macros perform similarly across different densities. This translates to saving months of design cycle and development time for our customers.

Advanced Technology

Memory development can be concurrent with advanced process technology development ensuring significant Time-to-Market advantages for our customers.


		RegiRAM : Bridging the Performance Gap Between Logic and Memory RegiRAM (Register RAM) is high density (multiple megabit), static memory that performs like a register file in speed, flexibility, and robustness. RegiRAM, like a register file, scales accordingly with logic as process technology progresses as shown in the figure below Key RegiRAM Features: · Sub-nanosecond access time with zero latency · Fully static, consumes little DC power · Consumes as little as one tenth of active power as conventional SRAM · Macro density is 1.5 to 2 times 6T/8T · Compiler-generated macros · Multiple-port Capable · ECC and/or redundancy options available for repair RegiRAM offers three times the performance, one-tenth the power, and up to two times higher density than the conventional 6T/8T single/dual port SRAM, and is ideal for System-On-Chip applications in Communications, Networking, Computing, and Consumer products. Unlike conventional memory that turns on the entire word line when reading data from memory cells, RegiRAM activates only very small amount of memory cells so the power consumption is extremely low and is essentially independent of the memory density used. Design Flexibility With its multiple-port capability, RegiRAM is especially ideal for those products which call for increasing demand of higher data throughput, and greater bandwidth, as in networking and high performance graphic applications. RegiRAM's flexibility also lies in its capability of achieving unprecedented peripheral efficiency even in distributed, small (Kb) memory blocks of different configurations. Other high-density memory solutions in the market not only become area-inefficient, when density becomes less than 1Mb, but also lacking in multiple-port capability. Superior Reliability Employing RegiRAM's unique register-file-like characteristics, differential sensing has been completely eliminated from the design, such that no sense amplifier is needed inside the memory. This results is a superior tolerance to noise, making RegiRAM far more robust and reliable than the conventional SRAM. RegiRAM also offers UniRAM's patented high performance ECC (Error Correction Code) circuit, which is capable of correcting data within one nanosecond of processing time, as an option for soft error recovery, making RegiRAM virtually immune to soft errors. Low Cost of Ownership With RegiRAM's ultra-high performance and ease of use, design complexity is dramatically reduced. Consequently, gate counts for glue logic, data paths, and buffers are also significantly reduced. This translates to die size reduction above and beyond that of a smaller memory macro area. RegiRAM uses standard logic process with no special process requirements, meaning no production cost adder over logic wafers. Compiler-Based RegiRAM macros are compiler-generated, and optimized for performance and density. Compiler-produced macros perform similarly across different densities. This translates to saving months of design cycle and development time for our customers. Advanced Technology Memory development can be concurrent with advanced process technology development ensuring significant Time-to-Market advantages for our customers.



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